Background of the Invention
1. Field of the Invention
The present invention relates to LSI technology in general and in particular to CMOS receivers that receive signals from other circuit families such as TTL.
2. Prior Art
It is well known in the prior art to use a CMOS receiver to interface other circuit families including TTL logic with CMOS logic. The first stage of most CMOS receivers is a simple CMOS inverter consisting of a PFET device connected in series to a NFET device. Depending on process variation, among other things, the input voltage at which the output of the CMOS inverter switches can vary as much as 700 or 800 mV. Due to this variation, the switch point of the CMOS inverter tends to be unstable. The instability has an adverse effect on the use of the CMOS inverter to interface TTL circuits with CMOS circuits.
The straightforward approach for designing the input stage of the CMOS receiver is to set the switch point of the input stage to be halfway between V.sub.IL and V.sub.IH, where V.sub.IL represents the low input voltage and V.sub.IH represents the high input voltage, of the logic technology to which the input stage is connected. In the case of TTL input logic signals, the switch point of the CMOS inverter is set at approximately 1.4 volts. The TTL signals also have excursions about the 1.4V switch point. The excursions provide noise immunity for the TTL signals. Stated another way, the excursions allow the TTL circuit to function satisfactorily in relatively noisy environments. However, if TTL circuits are interfaced with CMOS logic circuits the inherent excursions which occur about the threshold switch point of the CMOS inverter reduce or even eliminate the TTL noise margin. Therefore, there is a need to provide a device which stabilizes the threshold switch point of the CMOS receiver.
U.S. Pat. Nos. 4,584,492 and 4,673,021 describe circuit arrangements with feedback systems which compensate and/or stabilize the switch point of a CMOS inverter. Even though the patents work well for their intended purposes, the circuit arrangements use relatively large areas of silicon chips. In addition, the feedback loops have to be stabilized over all operating frequencies and temperature ranges.
U.S. Pat. No. 4,719,369 sets forth a driver circuit in which the gate width of the output transistors in a series connected PFET device and NFET device is regulated so that the output resistance of said drive circuit matches the impedance of the driven transmission line.
U.S. Pat. No. 4,424,456 describes a CMOS driver circuit for driving a CCD load. The rise and fall times of the drive pulses are controlled to generate pulses that are more effective in driving the CCD load. In one of the embodiments, the fall time of the pulses is controlled by setting the overall value of the (W/L) ratio of transistors in the discharge path.